Clock Generator: From PLL Fundamentals to Selection and Procurement

2026-10-22

A clock generator is the core of a system's timing architecture, responsible for establishing and distributing a unified timing reference. Its function is to convert a single reference clock source into multiple synchronized clock signals with different frequencies and different logic levels.

This is achieved primarily through an on-chip phase-locked loop (PLL): the phase frequency detector (PFD) continuously compares the phase and frequency of the reference input against the feedback divided signal, and the resulting phase error is converted by the charge pump and loop filter into a control voltage that tunes the output frequency of the voltage-controlled oscillator (VCO), satisfying f_OUT = f_IN × N / R. The integer division ratio N can be extended to a fractional form through Σ-Δ (Sigma-Delta) modulation, enabling high-precision non-integer frequency multiplication and significantly improving output frequency resolution.

Loop bandwidth is a key parameter that requires careful trade-offs in PLL design. Its value has opposite suppression effects on reference clock noise and VCO noise: a wider bandwidth suppresses the close-in noise of the VCO but lets jitter on the reference through; a narrower bandwidth filters out reference noise, but locking becomes slower and out-of-band phase noise degrades. In addition, the physical implementation of the VCO directly determines its phase noise floor: an LC-tank-based VCO is typically about 10 dBc/Hz lower than a ring oscillator (typical value), at the cost of a larger on-chip inductor area.

In practical applications, clock generators cover virtually all high-speed interconnect scenarios, including but not limited to: PCIe Gen1–6 reference clocks, 125 MHz and 156.25 MHz for Ethernet PHYs, FPGA configuration and logic clocks, optical modules and SSD controllers, as well as device clocks and SYSREF in JESD204B/C systems. It must be emphasized that a clock generator integrates a complete PLL architecture with frequency synthesis and dynamic frequency scaling capability, whereas a clock buffer only performs signal fanout expansion and level shifting. The two have clearly distinct roles in the system architecture and are not interchangeable.

Frequently Asked Questions (FAQ)

Q1: No output after power-up? First measure the voltage and ripple on every VDD/VDDO rail, then use a 10× probe to check whether the crystal is oscillating — a load capacitance that does not match the crystal's nominal CL and a solder bridge between XIN and XOUT are the most common causes. Next, capture the I²C/SPI waveform to confirm the address and ACK, and read the status register to determine whether the device is held in reset or output mute.

Q2: LOL stays active, PLL fails to lock? Verify item by item that the reference clock amplitude and frequency meet specification, that the target VCO frequency falls within the device range and is not near either edge, and that the loop filter resistor and capacitor values match the recommended values. For multi-PLL devices, also check the initialization sequence of the two PLL stages, and confirm that the exposed pad is reliably grounded through a dense via array.

Q3: Measured jitter far worse than the datasheet? This mostly stems from power supply and layout. Place a 0.1 µF ceramic capacitor within 5 mm of each power pin, supplemented by a 1–10 µF bulk capacitor; keep differential pairs strictly length-matched with continuous impedance and minimal vias, and route them away from switching power supplies and high-speed digital traces.

Q4: Can spread-spectrum clocking (SSC) be enabled directly? The typical configuration is −0.5% down spread with a 30–33 kHz modulation rate. It significantly reduces EMI peaks, but introduces tracking skew in downstream PLLs (on the order of a hundred picoseconds at 30 kHz modulation).

Market Landscape

The global clock generator IC market stood at approximately USD 730 million in 2025 and is expected to expand moderately at a CAGR of about 5.6%. Infineon, Texas Instruments, Renesas, Microchip and Skyworks together account for more than half of the market. In addition, SiTime has carved out a differentiated track by replacing quartz crystals with MEMS resonators, offering advantages in vibration resistance and cold-temperature startup reliability, with integrated jitter on its high-end parts reaching down to 85 fs. Domestic vendors are moving quickly along the path of PCIe Gen 5–7 compliance and pin-to-pin replacement of international part numbers, providing new options for balancing supply chain resilience against cost.

Selection Guidelines and Featured Models

Selection can be condensed into five core criteria: frequency and channel count; whether jitter/phase noise meets the protocol budget; logic level and multi-voltage compatibility; temperature range and qualification (industrial −40 to 85 °C, automotive requires AEC-Q100); and package and lifecycle.

The table below summarizes eight representative clock generators as a selection reference.

Part Number	Manufacturer	Output Channels	Frequency Range	Jitter Performance	Package
CDCM61001	TI	1 output (LVPECL/LVDS/2×LVCMOS)	43.75–683.264 MHz	0.509 ps RMS typ.	32-QFN
Si5341	Skyworks (formerly Silicon Labs)	10 differential	100 Hz–1028 MHz	90 fs RMS typ.	64-QFN
Si5338	Skyworks (formerly Silicon Labs)	4 differential / 8 single-ended	0.16–710 MHz	0.7 ps RMS typ.	24-QFN
RC21012	Renesas (VersaClock 7)	12 differential, 24 channels total	LVDS/LP-HCSL up to 650 MHz	150 fs class	48-VFQFPN
9FGL0441DKILF	Renesas	4 LP-HCSL + 1 LVCMOS	25 / 100 MHz, PCIe Gen1–6	90 fs RMS	32-VFQFPN
NB3N51034	onsemi	4 HCSL/LVDS	100 or 200 MHz	Phase noise −138 dBc/Hz @ 1 MHz	TSSOP-20
LMK04828	TI	14 differential + 7 SYSREF	Up to 3.2 GHz	88 fs RMS	64-WQFN
AD9528	ADI	14 LVDS/HSTL	6 outputs up to 1.25 GHz, 8 outputs up to 1 GHz	<160 fs @ 122.88 MHz	72-VFQFN

When substituting, note that similar functionality does not mean a part can be swapped in directly. For example, both the AD9528 and the LMK04828 target JESD204B/C, but their pin definitions, loop filter requirements and register maps all differ, so a board respin and firmware rewrite are mandatory. Even for parts claimed to be pin-to-pin, verify the default output impedance, control interface address and configuration tool chain — an incompatible configuration software flow will equally stall production.

Procurement and Supply Chain

SEMICONE is an ISO 9001 certified independent electronic components distributor, providing BOM matching, sourcing of hard-to-find and obsolete parts, quality inspection, logistics compliance and counterfeit avoidance and detection. Its Clock/Timing category lists parts such as the Renesas RC21012, 9FGL0441DKILF, the onsemi NB3L553 series and the ADI LTC6947, with quotation support. When purchasing clock chips, pay particular attention to verifying the marking and lot code to prevent pulled or refurbished parts from entering the supply chain.

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