Google Partners with Marvell to Develop Two New AI Chips
2026-04-21
In April, multiple reports indicated that Google is in advanced negotiations with U.S. chip design giant Marvell Technology to co-develop two custom chips optimized for AI inference. This collaboration marks a critical step by Google in diversifying its AI chip supply chain and reducing reliance on single suppliers.
Synergistic Design: MPU and Next-Gen TPU
The second chip is a next-generation TPU specifically optimized for AI inference workloads. Compared to the current flagship TPU v7, this new TPU will be deeply tailored for inference use cases, targeting better cost-performance ratios to reduce the compute cost per AI response. Google reportedly plans to produce nearly 2 million MPUs, though sources note this figure could change as negotiations remain in early stages.
Supply Chain Diversification and Competitive Pressure
From a strategic perspective, Google is systematically building a diversified custom-chip supply chain. Previously, Google had long collaborated with Broadcom on TPU development and partnered with MediaTek on related projects. Marvell's addition expands its roster of design partners from two to three and introduces the MPU as a new chip category.
Google's push to accelerate this collaboration is partly driven by competitive pressure from NVIDIA. According to an internal employee, Google already had plans for inference-specific chips, but accelerated these efforts following NVIDIA's announcement of its Language Processing Unit (LPU) at the GTC conference in March. Notably, Marvell was the chip design partner for Groq's first-generation LPU, indicating Marvell possesses hands-on experience in designing inference-optimized silicon.
Timeline and Strategic Trends
Under this arrangement, Marvell will serve in a design services role, similar to its involvement in Google's Axion ARM CPU project. The two companies aim to finalize the MPU design by 2027 at the earliest, after which it will enter trial production. Details regarding the completion timeline and planned production volume for the second chip—the new inference-focused TPU—remain unclear.
As AI user bases continue to expand, inference costs have become the fastest-growing component of data center operating expenses. By developing custom chips, Google seeks to lower these costs and improve the return on investment for its AI initiatives. This partnership represents a significant step in Google's broader strategy to diversify its AI silicon portfolio, aiming to optimize inference performance, reduce operational expenditures, and solidify its competitiveness in AI infrastructure.
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