onsemi EPP Platform: Reconstructing Power Packaging Architecture with 12-Inch Silicon Wafers
2026-09-17
As rack power density in AI data centers continues to climb and efficiency requirements for electric vehicle traction inverters become increasingly stringent, traditional power electronics packaging is approaching its physical limits. On September 16, onsemi officially launched its Embedded Power Platform (EPP), transforming packaging from a passive physical enclosure into an active performance enhancer and using the 12-inch silicon wafer itself as the packaging carrier.
Heterogeneous silicon, silicon carbide (SiC), and gallium nitride (GaN) dies are embedded directly into cavities in the wafer and interconnected through precisely patterned wafer-level copper redistribution layers (RDL) and vertical vias, completely eliminating traditional wire bonding. Because key assembly steps are completed inside a controlled semiconductor fab, cleanroom manufacturing precision can be applied directly to power system integration.
Coordinated Breakthroughs in Electrical and Thermal Performance
Architectural Advantages
The architectural advantages of EPP have already translated into quantifiable benefits in practical applications. In an early solid-state circuit breaker design for AI systems, an EPP-based solution reduced size by about 50% and operating temperature by about 20% compared with conventional designs. For EV traction inverters, EPP can deliver up to 4x higher power density and 15% lower power loss, while its scalable architecture supports a single inverter platform from low-end to high-end, helping automakers reuse designs across vehicle models and reduce R&D and manufacturing costs.
Notably, Subaru has become one of EPP's first early partners and is working with onsemi to evaluate how the platform can support future electrified vehicle architectures. EPP is planned to begin delivering engineering samples to strategic partners in the automotive and AI ecosystems in 2026.
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