Model No: SPC564A80L7CFAR
STMicroelectronics SPC564A80L7CFAR
Manufacturer: STMicroelectronics
SEMICON NO.: SPC564A80L7CFAR
Package: 176-LQFP
Stock: In stock
Description: e200z4 SPC56 MCU IC 32-Bit 150MHz 4MB FLASH
SEMICON NO.: SPC564A80L7CFAR
Package: 176-LQFP
Stock: In stock
Description: e200z4 SPC56 MCU IC 32-Bit 150MHz 4MB FLASH
Quantity :
| Mfr | STMicroelectronics |
| Device Type | 32-bit Automotive Microcontroller |
| Product Family | SPC56 |
| Core Processor | e200z4 |
| Core Size | 32-bit Single-Core |
| Maximum CPU Speed | 150 MHz |
| Program Memory (Flash) | 4 MB (4M × 8) |
| RAM | 192 KB on-chip RAM |
| Instruction Cache | 8 KB |
| eTPU Code/Data RAM | 14 + 3 KB |
| DMA | 64-channel DMA |
| Interrupt Controller | Configurable |
| Memory Protection | 16-entry MPU |
| Supply Voltage (Vcc/Vdd) | 1.14 V to 1.32 V |
| Operating Temperature | –40°C to +125°C |
| Package | 176-LQFP |
| Mounting Type | Surface Mount |
| Compliance | RoHS Compliant |
SPC564A80L7CFAR 32-Bit Power Architecture Automotive MCU
The SPC564A80L7CFAR is an AEC-Q100 qualified 32-bit Power Architecture microcontroller from STMicroelectronics for automotive powertrain, transmission and body control. Built on a 150 MHz e200z4 core with Variable Length Instruction Encoding, a superscalar design with two execution units and DSP instructions, it executes up to two integer or floating-point operations per cycle. On chip are 4 MB of ECC flash with Read-While-Write, 192 KB of SRAM (32 KB standby), an 8 KB instruction cache and a 5 x 4 crossbar switch. Networking spans three FlexCAN channels, a FlexRay V2.1 controller, three eSCI and three DSPI interfaces, alongside dual 12-bit queued ADCs. Housed in a 24 x 24 mm 176-pin LQFP rated -40 C to +125 C, it is a robust real-time control platform.
The SPC564A80L7CFAR is an AEC-Q100 qualified 32-bit Power Architecture microcontroller from STMicroelectronics for automotive powertrain, transmission and body control. Built on a 150 MHz e200z4 core with Variable Length Instruction Encoding, a superscalar design with two execution units and DSP instructions, it executes up to two integer or floating-point operations per cycle. On chip are 4 MB of ECC flash with Read-While-Write, 192 KB of SRAM (32 KB standby), an 8 KB instruction cache and a 5 x 4 crossbar switch. Networking spans three FlexCAN channels, a FlexRay V2.1 controller, three eSCI and three DSPI interfaces, alongside dual 12-bit queued ADCs. Housed in a 24 x 24 mm 176-pin LQFP rated -40 C to +125 C, it is a robust real-time control platform.
Highlights and Features
● 150 MHz e200z4 core with VLE, superscalar dual-execution-unit design and DSP instructions.
● 4 MB ECC flash with Read-While-Write, 192 KB SRAM (32 KB standby) and an 8 KB instruction cache.
● 5 x 4 crossbar switch, 24-entry MMU and an External Bus Interface (EBI).
● Fail-safe support: 16-entry MPU, a three-module CRC unit and a junction temperature sensor.
● 64-channel DMA plus a configurable interrupt controller with a non-maskable interrupt input.
● 3 x eSCI, 3 x DSPI (two with Micro Second Channel) and 3 x FlexCAN with 64 message buffers each.
● 1 x FlexRay V2.1 up to 10 Mbit/s with 128 message objects for deterministic in-vehicle networking.
● Timer complex: 24-channel eMIOS, 32-channel eTPU2 and a 6-channel reaction module.
● Dual 12-bit queued ADCs (40 channels, expandable to 56), 688 ns minimum conversion.
● 4-40 MHz oscillator, FMPLL, boot assist module, Nexus Class 3+ debug and 120 GPIO.
Applications
● Powertrain and engine management: injection, ignition and combustion control.
● Transmission and hybrid or electric drivetrain control units.
● Body control, chassis and domain controllers requiring high integration.
● Motor and actuator control using the eTPU2 and eMIOS timing resources.
● Automotive gateways built on FlexRay, FlexCAN and the EBI.
Frequently Asked Questions
Q: How much memory is available? A: 4 MB of ECC flash with Read-While-Write, 192 KB of SRAM (32 KB standby) and an 8 KB instruction cache.
Q: Which in-vehicle networks are supported? A: Three FlexCAN channels with 64 buffers each, a FlexRay V2.1 controller to 10 Mbit/s, three eSCI/LIN and three DSPI.
Q: What are the key precautions? A: Decouple the 1.14-1.32 V core and 3.3 V/5 V I/O rails, observe MSL 3 floor life and follow the ECC and boot guidelines.
Alternative and Equivalent SPC56 microcontroller Models
● SPC564A80L7CFBR - the same 4 MB, 176-pin LQFP device at a later silicon revision, a drop-in replacement on the identical footprint.
● SPC564A80L7CFCR - the C revision of the same 4 MB powertrain MCU for designs needing the newest silicon.
● SPC564A80B4 - the same 4 MB device in the alternate package and feature variant for platforms standardised on that option.
● SPC564A70L7CFBR - a 2 MB, 120 MHz member of the same SPC56 A line in the identical 176-pin LQFP for lower-cost derivatives.
● SPC564A70L7COBR - the 2 MB, 120 MHz version with a different feature option for specific powertrain platforms.
● 150 MHz e200z4 core with VLE, superscalar dual-execution-unit design and DSP instructions.
● 4 MB ECC flash with Read-While-Write, 192 KB SRAM (32 KB standby) and an 8 KB instruction cache.
● 5 x 4 crossbar switch, 24-entry MMU and an External Bus Interface (EBI).
● Fail-safe support: 16-entry MPU, a three-module CRC unit and a junction temperature sensor.
● 64-channel DMA plus a configurable interrupt controller with a non-maskable interrupt input.
● 3 x eSCI, 3 x DSPI (two with Micro Second Channel) and 3 x FlexCAN with 64 message buffers each.
● 1 x FlexRay V2.1 up to 10 Mbit/s with 128 message objects for deterministic in-vehicle networking.
● Timer complex: 24-channel eMIOS, 32-channel eTPU2 and a 6-channel reaction module.
● Dual 12-bit queued ADCs (40 channels, expandable to 56), 688 ns minimum conversion.
● 4-40 MHz oscillator, FMPLL, boot assist module, Nexus Class 3+ debug and 120 GPIO.
Applications
● Powertrain and engine management: injection, ignition and combustion control.
● Transmission and hybrid or electric drivetrain control units.
● Body control, chassis and domain controllers requiring high integration.
● Motor and actuator control using the eTPU2 and eMIOS timing resources.
● Automotive gateways built on FlexRay, FlexCAN and the EBI.
Frequently Asked Questions
Q: How much memory is available? A: 4 MB of ECC flash with Read-While-Write, 192 KB of SRAM (32 KB standby) and an 8 KB instruction cache.
Q: Which in-vehicle networks are supported? A: Three FlexCAN channels with 64 buffers each, a FlexRay V2.1 controller to 10 Mbit/s, three eSCI/LIN and three DSPI.
Q: What are the key precautions? A: Decouple the 1.14-1.32 V core and 3.3 V/5 V I/O rails, observe MSL 3 floor life and follow the ECC and boot guidelines.
Alternative and Equivalent SPC56 microcontroller Models
● SPC564A80L7CFBR - the same 4 MB, 176-pin LQFP device at a later silicon revision, a drop-in replacement on the identical footprint.
● SPC564A80L7CFCR - the C revision of the same 4 MB powertrain MCU for designs needing the newest silicon.
● SPC564A80B4 - the same 4 MB device in the alternate package and feature variant for platforms standardised on that option.
● SPC564A70L7CFBR - a 2 MB, 120 MHz member of the same SPC56 A line in the identical 176-pin LQFP for lower-cost derivatives.
● SPC564A70L7COBR - the 2 MB, 120 MHz version with a different feature option for specific powertrain platforms.
