Model No: PI6CEQ20200LIEX
Diodes Incorporated PI6CEQ20200LIEX
Manufacturer: Diodes Incorporated
SEMICON NO.: PI6CEQ20200LIEX
Package: 20-TSSOP
Stock: In stock
Description: PCIe Buffer IC 110MHz 1 Circuit
SEMICON NO.: PI6CEQ20200LIEX
Package: 20-TSSOP
Stock: In stock
Description: PCIe Buffer IC 110MHz 1 Circuit
Quantity :
| Mfr | Diodes Incorporated |
| Device Type | PCIe Gen2/Gen3 Zero-Delay Buffer / Clock Buffer |
| Number of Circuits / PLL | 1 |
| Supply Voltage | 3.135 V to 3.465 V (3.3V nominal) |
| Maximum Output Frequency | 110 MHz |
| Input / Output Type | HCSL |
| Differential - Input:Output | Yes / Yes |
| Ratio - Input:Output | 1:2 |
| Operating Temperature | -40°C to +85°C |
| Package | 20-TSSOP |
| Mounting Type | Surface Mount |
| Compliance | RoHS Compliant |
PI6CEQ20200LIEX is a high‑performance PCIe Gen2 / Gen3 zero‑delay clock buffer manufactured by Diodes Incorporated, supplied in tape‑and‑reel 20‑pin TSSOP surface‑mount package. This PLL‑based timing IC features one differential HCSL clock input and two independent HCSL outputs, built‑in signal equalization circuitry and dual‑bandwidth PLL for spread‑spectrum clock tracking, running from 3.135 V‑3.465 V single power rail, achieving typical 40 ps cycle‑to‑cycle jitter and below 10 ps output‑to‑output skew, and supporting stable operation over industrial temperature range of ‑40 °C to 85 °C for long‑trace clock distribution on server, network and embedded PCI‑Express hardware boards.
Key Features
● Built‑in proprietary signal equalization technology to compensate signal attenuation over long clock routing traces and improve high‑speed signal integrity.
● 1‑to‑2 differential clock distribution with two HCSL‑level outputs for duplicating the main reference clock signal.
● Dual‑selectable PLL bandwidth setting that accurately tracks spread‑spectrum clock (SSC) for electromagnetic‑interference reduction.
● Ultra‑low clock jitter of 40 ps typical cycle‑to‑cycle value and less than 10 ps skew between the two output channels.
● Single 3.3‑volt power‑supply operation with allowed tolerance range from 3.135 V to 3.465 V.
● Output‑enable control pins allowing designers to shut down unused clock channels for power saving.
FAQ
Q: What advantage does internal equalization bring?
A: It recovers degraded clock signals after long‑distance transmission and maintains reliable PCIe timing performance.
Q: Can this chip generate a new independent clock frequency?
A: No, it is a zero‑delay buffer that copies and distributes the input clock without frequency multiplication.
Alternative clock chips
1. PI6CEQ20200LI: Pin‑compatible zero‑delay PCIe clock buffer supplied in tube packaging, an alternative choice for small‑batch prototype assembly.
2. 9DB102BGLFT: High‑speed 1‑to‑2 PCIe zero‑delay clock buffer from another vendor, serving as cross‑brand functional replacement for clock‑distribution circuits.
3. PI6CEQ20400LIEX: Four‑output PCIe zero‑delay buffer with identical equalization feature, an upgraded option when more duplicated clock outputs are required.